Systolic VLSI chip for implementing orthogonal transforms, A

Includes bibliographical references.This paper describes the design of a systolic VLSI chip for the implementation of signal processing algorithms that may be decomposed into a product of simple real rotations. These include orthogonal transformations. Applications of this chip include projections, discrete Fourier and cosine transforms, and geometrical transformations. Large transforms may be computed by "tiling" together many chips for increased throughput. A CMOS VLSI chip containing 138 000 transistors in a 5x3 array of rotators has been designed, fabricated, and tested. The chip has a 32-MHz clock and performs real rotations at a rate of 30 MHz. The systolic nature of the chip makes use of fully synchronous bit-serial interconnect and a very regular structure at the rotator and bit levels. A distributed arithmetic scheme is used to implement the matrix-vector multiplication of the rotation.This work was supported by Ball Aerospace, Boulder, CO, and by the Office of Naval Research, Electronics Branch, Arlington, VA, under Contract ONR 85-K-0693

Limited-weight codes for low-power I/O

Capacitances for the I/O tend to be several orders of magnitude larger than for the internal circuit. Decreasing the number of transitions at the I/O will then translate into large savings in power dissipation for the entire circuit. A way of decreasing the number of transitions at the I/O at the expense of slightly increasing the number of internal transitions is to use coding. We propose a method that uses bit-encoding with transition signaling and word-encoding with limited-weight codes. By a proper choice of the limited-weight code parameters different I/O transition activity values can be obtained. For n 2 -limited-weight codes, theoretical results similar to the previously proposed Bus-Invert method are obtained. 1 Introduction Compared to other technologies like TTL or ECL, CMOS is a low-power technology. This is especially true when one looks at the standby or static power dissipation which is practically nil for static CMOS. The problem is that because of shrinking device ..

Synchronous Up/Down Counter with Period Independent of Counter Size

The theory and practice of up-only (or downonly) prescaled counters is well understood both in industry and in the academia but until now it was not known if the design of a prescaled up/down binary counter is possible. This paper presents the theory behind building such a synchronous up/down counter of arbitrary length and with period independent of counter size by describing the design of a 64-bit up/down counter running at 40MHz implemented in an Atmel AT6000 SRAM-based FPGA. The main idea behind the novel up/down counter design is to recognize that the only extra difficulty with an up/down (vs. an up-only or down-only) constant time counter is when the counter changes "state" from counting up to counting down and vice-versa. For dealing with this difficulty the new design uses a "shadow" register that is always kept loaded with the previous counter value. When counting only up or only down the counter functions like a normal up-only or downonly prescaled counter but when it changes..

Low-Power Encodings for Global Communication in CMOS VLSI

Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space [30]. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tri-state on-chip buses with level or transition signalin..